Peter Debacker

Peter Debacker received the M.Sc. (Hons.) degree in electrical engineering from the Katholieke Universiteit Leuven, Leuven, Belgium, in 2004. He was with Essensium, Leuven. He joined IMEC, Leuven, in 2011, where he is currently a R&D Team Leader in the Semiconductor Technology and Systems division. He leads a team that evaluates key power-Performance-area (PPA) benefits of scaled CMOS technologies (5nm, 3nm and beyond) and beyond CMOS technologies, and develops technology, architecture and algorithms for various machine learning techniques like ConvNets, Temporal Predictions, Anomaly Prediction etc. In his past he has worked on IMEC’s low-power digital chip and processor architectures and implementation in advanced technology nodes.