How Complex Machine Learning Will Enter Your Smartphone

How Complex Machine Learning Will Enter Your Smartphone

Artificial Intelligence (AI) and Machine Learning (ML) are amongst the emerging trends in Business and Marketing. Yet, a lot of this cleverness is located in the Cloud. Read: in big server parks with high-end processing capabilities. In a not too distant future, several applications will enter our lives that require an increased amount of intelligence and computation being implemented closer to the user. Be it for reasons of speed, energy-efficiency or privacy. Think about self-driving vehicles who have to respond more quickly than the time it takes to send data up and down to the Cloud. Or privacy-sensitive tasks as Voice analysis and face- or fingerprint recognition, for which legal or user constraints might keep you from sending data over the air. In a way, this leads to the question we engineers are now facing: ‘How to get a server rack in your back pocket’?

In the pursuit to enable increased computational complexity in smaller and mobile devices, the high-tech industry has two main angles of attack: through hardware and through software. In the software domain, computational concepts with sounding names as “Deep Neural Network (DNN) engines” and “Spiking Neural Networks (SNN)” already exist. They are part of a field of expertise called “Neuromorphic Computing”. Mimicking aspects of how the Human brain works, they give rise to promising low-power algorithms capable of dealing with complex tasks. It’s now up to the hardware guys active in neuromorphic computing to follow suit.

How can we develop low-power, preferably battery-powered, hardware capable of running these state-of-the-art algorithms? The answer to this question is multi-facetted and needs to be tackled from the materials- and processing angle over processor- and memory design up to system-level optimizations. In other words: it’s one of these journeys where multiple brains can accomplish more than one. And that’s exactly why imec has teamed up with in total nineteen organizations from research and industry to develop the hardware solutions for these next-generation Artificial Intelligence and Machine Learning systems. In April this year, we started the EU-funded project called TEMPO (Technology and hardware for nEuromorphic computing/received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 826655). With our combined efforts, we will in this three-year program center our activities around 8 different use cases, ranging from consumer to automotive and medical applications. For example, traffic recognition in autonomous vehicles, advanced sensing capabilities for drones, applications in food classification, etc.

The project will focus on scanning and evaluating several of the materials and technology options that already exist within each of our organizations. Substantial effort will also go into the development of new memory technologies, including how to efficiently integrate them with processing blocks on highly advanced, yet low-power, computer chips. And all of this with industrial manufacturing in mind. Allowing these novelties to quickly become available in the market.

Once successfully implemented together with the latest and greatest in AI and ML software, technology will become available that opens up possibilities for user interaction that now can only be executed in the Cloud. No doubt this will also impact the domains of Retail, Marketing and many more. As always, we have exciting times ahead and future will tell…

Read More: AI + Intent Data: The Key to Ending Inefficient Marketing Tactics

Picture of Peter Debacker

Peter Debacker

Peter Debacker received the M.Sc. (Hons.) degree in electrical engineering from the Katholieke Universiteit Leuven, Leuven, Belgium, in 2004. He was with Essensium, Leuven. He joined IMEC, Leuven, in 2011, where he is currently a R&D Team Leader in the Semiconductor Technology and Systems division. He leads a team that evaluates key power-Performance-area (PPA) benefits of scaled CMOS technologies (5nm, 3nm and beyond) and beyond CMOS technologies, and develops technology, architecture and algorithms for various machine learning techniques like ConvNets, Temporal Predictions, Anomaly Prediction etc. In his past he has worked on IMEC’s low-power digital chip and processor architectures and implementation in advanced technology nodes.

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